Design Verification Job Vacancy in Futures and Careers Bengaluru, Karnataka – Updated today

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Full Details :
Company Name : Futures and Careers
Location : Bengaluru, Karnataka
Position :

Job Description : Job Description
Roles and Responsibilities
Will be taking part ownership of existing UVM based testbench for project and make required enhancements to the testbench as required.

Develop testcases using the testbench. Create functional coverage items. Run code and functional coverage, analyse data and work with designer

To achieve desired coverage. Make required updated to testbench for netlist simulation, run identified tests on netlist and work with team for required debug.

Technical Skills

Well versed in full Verification cycle of including test development, debug and coverage closure through industry standard simulation tools.

Well versed with Cadence simulation tools (Xcelium and Simvision) and netlist simulation.

Familiarity with Datapath blocks is desirable.

Knowledge of scripting – python/shell.

Should be able to execute the tasks independently.
Requirements
Verification Engineer (Most needed, ever green)
Above verification with Low Power skills (additional)
Low Power Verification:
Good understanding on Design Verification and methodologies.

Verilog, SV and UVM.

Writing Testcase, Test plan.

Knowledge on Coverage.

Debugged Simulation Failures.

Understanding SOC and IP verification.

Protocols:
SPI/I2C/AXI/APB/AHB/PCIE/Ethernet/USB3.2/DDR5/LPDDR5
UVM:
UVM RAL/Register verification
Basics of a RDL (Register Definition Language) file
Backdoor register programming concepts
Hands on AXI/AHB/APB VIPs
Regression Management:
Intro to running regression.
Basics of Verification Plan (HPV) from SNPS
Basics of vManager from Cadence
How to triage the failures and see the top 3 failing signatures.
Intro to NLP simulations Flow and debugging NLP runs.
UPF structural knowhow

GenericSkills :

Perforce commands and directory structure
Unix/Linux commands
Make file based flow
Shell/Perl scripting
Gvim/Emacs text editor
Good knowledge of waveform debugging with Verdi
Gate Level Simulation.
Intro to GLS and why is it required in the verification flow
Zero delay simulation needs and concept
Structures of SDF (min/typ/max)
SDF back annotation
Setup/Info required for starting GLS
Basic concepts of XPROP (VCS XPROP)

Role:Test Analyst
Salary: Not Disclosed by Recruiter
Industry:Engineering & Construction
Functional Area:Engineering – Software
Role Category:Quality Assurance and Testing
Employment Type:Full Time, Permanent
Key Skills
ApbAxiNLPSimvisionVerilogAhbPCIEI2CSPIPython
Education
UG:Any Graduate
Company Profile
FUTURES AND CAREERS
FUTURES AND CAREERS is a company that has a definite purpose. We offer Recruitment and Training Services to Companies and Educational Institutions. Success and longevity is directly linked to our Clients’ happiness along with our service delivery. Having been market experts in the areas that we recruit and train, we build long-term futuristic relationships with Employers, Institutions and Candidates in order to seal Win-Win relationships!
Company Info
Recruiter Name:Pavithra DamodharanContact Company:FUTURES AND CAREERSTelephone:+91-XXXXXXXXXXWebsite:http://jobs.futuresandcareers.com

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